Pathology: Cyclical/Repetitive PLL Behaviors
Synonyms:PLL Divider cycling, short-term repetitive behavior
Found by: Repetitive Behavior Agent
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Summary Diagnosis and Suggested Solution Path

If you were directed here by M1 Oscilloscope Tools' Hidden Anomaly Locator (HAL), then this section contains suggestions for what might be happening in your waveform, and possible steps you can take to understand it further or resolve the problem.

"The clock on Ch. X appears to have a pattern that repeats every N cycles. This corresponds to a frequency of F." -- In PLLs that include a divider, it is very common that the output signal will display a pattern of repeating behavior with a length in cycles equal to the divider ratio. So if for example your PLL includes a divide-by-ten structure, it would not be unexpected for the output signal to have a 10-cycle long repeating pattern.

If the differences between the average-edge positions of each divider cycle is small with respect to the total jitter (i.e. there are no significant 'spikes' in the pattern), the contribution to the total jitter of this pathology is small and this warning can usually be safely ignored.

If the differences between the average-edge positions of each divider cycles are large (i.e. there is one or more 'spikes' in the pattern... or said another way, there are distinctly separate large-swing cycles and small-swing cycles, where the large-swing cycles are 2x or more larger than the small-swing cycles), the effect that is producing this difference is likely contributing a large amount of correctable jitter to the total jitter. This is often an indication that the divider circuit has been designed in a way that it contributes significant electrical disturbance to the PLL core on specific cycles/rollover-counts as it sequences through its count... the disturbance being sufficient to cause the PLL to shift that edge. The PLL then puts out an edge either significantly earlier or later than it should have. When this effect is significant, it is easily detected as a regular pattern of large vertical excursions in a period-vs-time view of the PLL output.

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>Repeating interval pathologies are one of the most common issues one will find in PLL parts intended for clock distribution and reception. A PLL output exhibiting this cyclical timing pathology will issue a cycle, or burst of cycles, of atypical length... long, short or both... periodically distributed through a population of much smaller cycles. The length of these patterns is generally related to either the divider sequence duration or a nearby device creating a cyclical electrical disturbance. Generally, if the duration of the repetition interval is 10's to low 100's of cycles, it is a "core effect"... commonly the design of the divider. If the duration is 1000's or more, it is normally a response to external noise. It is not uncommon for this pathology to occur in bursts.

The Repetitive Behavior Agent detects when a repeating pattern on the order of a few to a few 100 cycles exists in the Period trace of a Clock signal. This Agent does not look at Data signals, or at any measurement other than Period. An autocorrelation> function is used to determine the cycle offsets (if any) at which the signal is strongly self-similar.

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This pathology requires a real-time capture platform (e.g. an RT scope) to see both the cyclical behavior and any longer term timing issues superimposed on those. The most obvious presentation will be on some kind of time vs time graph (period vs time, instantaneous freq vs time, TIE). At a timescale that shows a small to moderate number of repetitions of the pattern, the existence of the pattern will often be visually apparent if the problem is significant, as in the example below where the repeating pattern of two very short cycles alternating with a pair of medium-short cycles is readily visible. Note that while this behavior generally presents as a steady repeating pattern, it is not uncommon for this to also occur in bursts.

When the Repetitive Behavior Agent detects a repeating pattern, a Clock Period TimeView will be opened, zoomed in to show a few repetitions of the pattern. The Markers will also be turned on and placed around a single repetition of the pattern, as shown in Summary Diagnosis above.

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This cyclical output deviation is most often the result of either the divider sequencing through its count in a way that electrically disturbs the core of the PLL at certain points in the count, or a nearby device creating a cyclical electrical disturbance sufficient to affect the output edge placement. Generally, if the duration of the repetition interval is 10's to low 100's of cycles, it is a "core effect"... commonly the design of the divider... certain rollover counts disturbing the core electrical environment. If the duration is 1000's or more, it is normally a response to external noise, but the opposite has also been observed. When bursting of the pattern is present (i.e. the cyclical pattern displays and then subsides over time), it has been the author's experience that it is an external trigger (noise).

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The principal impact of this pathology is that the effect which is causing the differences is responsible of a large fraction of the overall jitter. In the example below, note that the Worst-Offender analysis of the waveform shows that over 60% of the total jitter is due to the effects of the cyclical behavior. Clearly, correcting this effect will have a substantial benefit on the overall jitter budget.

PLL divider problems can also lead directly to failures in multiple ways:

1) Short cycles failure - if a particular cycle of the divider is putting out a period that is shorter than the critical path length of the associated combinational logic, data will not have sufficient time to propagate between state devices and may be misread at the far end.This is commonly known as a setup-time failure, and can also lead to metastability when the short cycle length is at the borderline between acceptable and too short.

2) Large displacement failure - it is common in PLLs with divider problems to see 'restoration strokes'; that is, a much too short cycle will generally be followed by a longer than normal cycle, and vice versa. This creates large cycle-to-cycle displacements in the pulse train, which can lead to a large displacement failure.

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Related Pathologies
Other anomalies with similar presentations.

PLL cyclical output behavior is generally more a "cause" than an "effect". It is likely that other agents in HAL can activate when this effect is present. These other agents can serve as a differential diagnosis to either confirm or invalidate PLL repeating intervals as a root cause. One of the key differentials is the relationship of the pathology cycle to the divider cycle. If they are identical, the PLL core is a highly likely location for the root cause. If they are different, the effect is likely external, but close by unless the cycle is close to the switching frequency of the power supply. Other HAL agents that may activate when PLL cyclical output behavior is present:

  • FFT Modulation: If the Repetitive Behavior Agent activates, it is possible that the FFT Modulation Agent will also activate and indicate a peak at the frequency F (as well as harmonics of F) noted in the HAL response dialog.
  • Multi-modal histogram: If the Repetitive Behavior Agent activates, it is possible that the Histogram Multi-Mode Agent will also activate and indicate multiple peaks in the Period histogram due to the differing average cycle lengths produced by the individual cycles of the divider circuit.
  • Metastability: If the nature of the repetitive behavior is such that the shortest cycles produced approach or fall below the critical path flight time, metastable behavior may begin to manifest and trigger the Metastability Agent.


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Suggested Solutions

While this can be a high-impact pathology, it also tends to be quite easily diagnosed and corrected. Solutions the author has seen include redesign of the PLL divider to sequence differently (e.g. gray code) or impact the core differently as it rolls over, and mitigation of external activity feeding in through the PLL power attachment points (e.g. filtering at the PLL and/or reducing the effect of the aggressor).

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Related Topics